Electronic systems can be employed in environments having higher reliability requirements than typical industrial applications. For example, some applications require an integrated circuit be “radiation hardened” (rad hard) with respect to ionizing radiation. One such application can be space applications. In many space applications there is an increasing demand for data processing and throughput along with reconfigurability for flexibility. Accordingly, field programmable gate arrays (FPGAs) are enjoying increased use in radiation challenged environments. In such applications, systems require some type of nonvolatile memory to store configuration data for configuring (and if necessary reconfiguring) the FPGA. Further, centralized processing in satellites has placed a higher demand on more capable processors and multitasking, leading to larger non-volatile storage requirements (such as 64 Mbits and higher).
One conventional space system non-volatile memory solution can use commercially screened “flash” electrically erasable read only memory (EEPROM) in combination with synchronous dynamic random access memory (SDRAM), operating as a “shadow” memory, storing data from flash memory for fast access by a processor/programmable logic device. Data stored in nonvolatile devices can include processor boot code and/or configuration data for an FPGA, or the like. A drawback to such conventional approaches is that they can be size, weight and power intensive solutions, all of which are undesirable, particularly in space applications.
A conventional system is shown in FIG. 15 and designated by the general reference character 1500. A system 1500 can include commercially screened NOR type flash integrated circuit (IC) devices 1599-0 to -2, for storing data in a nonvolatile fashion. Such nonvolatile data can be loaded into commercially screened SDRAM devices 1597-0 to -2. Flash devices (1599-0 to -2) can be powered down once data is loaded into the SDRAM devices (1597-0 to -2) for an improved total ionizing dose response.
In the system shown, flash devices (1599-0 to -2) and SDRAMs (1597-0 to -2) have a triple module redundancy (TMR) configuration, replicating data across three devices. An SDRAM voter 1595 can determine a read data value based on data from three different data paths.
Data from SDRAM voter 1595 can be provided to an FPGA 1593 device, and can include configuration data and/or instruction data (for a processing circuit embedded in, or created by programming the FPGA 1593).
Voltage regulators 1591-0/1 can regulate supply voltages to the various devices of the system 1500.
In some conventional systems, system storage can be capable of storing up to several gigabytes of data. One example of a high data storage system is shown in FIG. 16. A system 1600 can include a main memory 1689 and a radiation hardened processor 1687. A main memory 1689 can typically use up-screened commercially available NAND flash devices (1685-0 to -2) employing TMR techniques. Further, a complex error detection and correction (EDAC) circuit 1683 can be included to improve the reliability of data access operations.
A processor 1687 can include a logic unit 1681, registers 1679 and a cache memory 1677. In a conventional system like that of FIG. 16, one estimate places 50% of the memory used (not including logic) in overhead to maintain the aforementioned TMR and EDAC. While total radiation dose issues on commercial devices can be mitigated through shielding, such solutions can also be costly and/or increase weight.
In many high reliability systems, processors can require instruction and data sequences (code) to implement a desired functionality. Such code not only initializes the firmware (Interfaces), but can also provide the correct execution sequence to perform the various tasks desired from the processor system. One example of a conventional high reliability (e.g., rad hard) processor system is shown as 1700 in FIG. 17.
A system 1700 can include a processor subsystem 1773 having a processor 1787 can various other circuits and/or interfaces. The conventional system 1700 of FIG. 17 shows a watch dog timer, general purpose input/outputs (GPIO), serial interfaces (i.e., I2C, UART, SPI), a parallel interface (PCI master), and a parallel memory interface (DDR controller). SPI interface can be connected to two boot EEPROMs 1775-0/1. DDR controller can be connected to SDRAM voter 1795. SDRAM voter 1795 provides data from TMR configured SDRAM devices 1797-0 to -2. EEPROMs (1775-0/1) can be radiation hardened devices that store code for the processor sub-system 1773, and thus can be costly. Further, multiple EEPROM devices are needed since high reliability EEPROM density is can be relatively small (i.e., about ˜20 Mbit) as compared to commercial devices.